Pad invariant FPGA and ASIC devices
US7812458B2 · kind B2 · utility
7Cited by
73References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 19, 2007 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Nov 19, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A three dimensional semiconductor device, comprising: a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device; a plurality of pads having predetermined positions within the device; and a configuration memory circuit coupled to the programmable logic blocks having a plurality of fabricating methods without altering the predetermined positions of the pads and the circuit blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.