Bridge design for SD and MMC data buses
US7812640B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2009 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Aug 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit with bi-directional signal transmission, including a first signal source, for generating a first signal comprising one bit per clock cycle during a first plurality of clock cycles, a second signal source, for generating a second signal including one bit per clock cycle during a second plurality of clock cycles, a first buffer, coupled with the first signal source, that outputs the first signal when the first buffer is enabled, a second buffer, coupled with the second signal source, that outputs the second signal when the second buffer is enabled, and a plurality of logical gates, coupled with the first signal source, the second signal source, the first buffer and the second buffer, that control enablement of the first buffer and the second buffer, such that (i) at any given clock cycle at least one of the first buffer and the second buffer is disabled, and (ii) when the first buffer and said the buffer are both disabled, subsequent generation of a ‘0’ bit in the first signal or the second signal causes enablement of the first buffer or the second buffer, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.