Digital calibration techniques for segmented capacitor arrays
US7812678B2 · kind B2 · utility
4Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Dec 11, 2008 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Feb 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes phase detection circuitry that generates control signals in response to an input clock signal and a feedback clock signal. The apparatus also includes a clock signal generation circuit that includes fine and coarse capacitors. The clock signal generation circuit changes a capacitance of the capacitors that are affecting the output clock signal in response to a change in the control signals. The apparatus also includes measurement circuitry that determines a calibration number of the fine capacitors having a combined capacitance that most closely matches a capacitance of one of the coarse capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.