Event memory assisted synchronization in multi-GPU graphics subsystem
US7812849B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2006 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Nov 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are disclosed for synchronizing graphics processing events in a multi-GPU computer system. A master GPU renders a first image into a first portion of a master buffer associated with a display interface, and then writes a first predetermined value corresponding to the first image in a first memory unit. A slave GPU renders a second image into a slave buffer, and then transfers the second image to a second portion of the master buffer, and writes a second predetermined value corresponding to the second image in the first memory unit. The first and second predetermined values represent a queuing sequence of the rendered images. The master GPU flips the first image to display only after examining the first predetermined value in the first memory unit, and flips the second image to display only after examining the second predetermined value in the first memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.