Display panel with pins arrangement
US7812912B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 2007 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Oct 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09727
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display panel including a substrate and many driving chips is provided. The substrate has many pad regions located in a non-display region of the substrate. Each pad region has many first pins with the same length disposed therein, and a pin pitch between two adjacent first pins, a width of each of the first pins, or both the pin pitch and the width vary with the positions where the first pins are disposed in the corresponding pad region. The driving chips are disposed in the non-display region of the substrate. Each driving chip has many second pins, and each second pin is electrically connected to each first pin correspondingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.