Method and apparatus providing rapid end-to-end failover in a packet switched communications network
US7813263B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2004 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Mar 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/28
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A hardware-based failover scheme enabling rapid end-to-end recovery is provided. Hardware logic periodically generates, transmits, receives, and processes heartbeat packets, sent from one end of the communications network to another, and then returned back. If a communications network node or communications link failure is being experienced along the transport path, then the hardware logic rapidly swaps the affected traffic conveyed to a pre-established backup transport path, typically within microseconds. Advantages are derived from the rapid failover effected end-to-end which enables continued delivery of provisioned communications services improving the resiliency and/or availability of a communications network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.