Programmable logic systems and methods employing configurable floating point units
US7814136B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2006 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | May 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.