PCI bus burst transfer sizing
US7814258B2 · kind B2 · utility
2Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2008 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Apr 15, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various apparatuses, methods and systems for specifying memory transaction sizes on a PCI bus are disclosed herein. For example, some embodiments of the present invention provide apparatuses for transferring data including a PCI bus, a memory map for memory transactions performed on the PCI bus, and at least one set of control registers adapted to establish at least one window within the memory map. The set of control registers contains an address range for the at least one window within the memory map and a burst transfer size for memory transactions taking place on the PCI bus that are addressed within the address range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.