Patent · US Active

System and method for adaptive power management based on processor utilization and cache misses

US7814485B2 · kind B2 · utility

23Cited by

8References

27Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Bryan C. Morgan · Leominster, US
Premanand Sakarda · Acton, US
Priya Vaidya · Shrewsbury, US
Yi Ge · Beijing, CN
Zhou Gao · Shanghai, CN
Swee-chin Pang · Austin, US
Manoj Thadani · Marlborough, US
Canhui Yuan · Shanghai, CN

Key dates

Filing date	Dec 7, 2004
Grant date	Oct 12, 2010
Priority date	—
Expiry date	Jul 15, 2029

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processing system may include a performance monitoring unit (PMU), a machine accessible medium, and a processor responsive to the PMU and the machine accessible medium. Instructions encoded in the machine accessible medium, when executed by the processor, may determine whether performance details for the processing system should be collected, based at least in part on a predetermined monitoring policy for the processing system. The instructions may generate performance data for the processing system, based at least in part on data obtained from the PMU. The instructions may determine whether the processing system should be reconfigured, based at least in part on the performance data and a power policy profile for the processing system. The instructions may automatically adjust power consumption of the processing system by using the PMU to reconfigure the processing system. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.