MOSFETS comprising source/drain recesses with slanted sidewall surfaces, and methods for fabricating the same
US7816261B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2007 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Jan 29, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/902
Abstract
The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.