Offset voltage correction circuit and class D amplifier
US7816992B2 · kind B2 · utility
9Cited by
9References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2007 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Jul 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/217
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An offset voltage correction circuit for a differential amplifier comprising NMOS transistors serving as a pair of differential transistors, and PMOS transistors serving as a pair of load transistors connected between outputs of the pair of differential transistors and a power source. The offset voltage correction circuit is equipped with a voltage generator for generating, between a source of any one of the pair of load transistors and the power source, a constant voltage for correcting an offset voltage of the differential amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.