Optimum timing of write and read clock paths
US7818135B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2008 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Mar 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for timing calibration of write and read-back data exchanges between respective dies of an external memory/external device has a master arbiter or, alternatively, a test bus between a system bus master interface and an external memory controller for driving the external memory/external device, a calibration circuit under control of the master arbiter via a test bus master interface to provide stepped-through time delays for test data exchanges between the dies, and the calibration circuit obtains pass/fail data indicating pass or fail of the varied time delays for the test data exchanges. A processor system at the system bus master interface selects calibration values corresponding to pass data, and applies the calibration values to the respective dies for timing of write and read-back data exchanges between the dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.