Processor system management mode caching
US7818496B2 · kind B2 · utility
2Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2007 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Dec 10, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, an apparatus comprises one or more processors supporting a system management mode, system management memory, and software controllable caching of memory, one or more memory modules, a memory controller, and a communication bus to couple the one or more memory modules to the memory controller. Other embodiments may be described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.