Method and apparatus for efficient resource utilization for prescient instruction prefetch
US7818547B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2008 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Aug 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38585
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculative thread instruction stream. The map table includes a yes-a-thing bit to indicate whether the associated physical register's content reflects the value that would be computed by the main thread. A thread progress beacon table is utilized to track relative progress of a main thread and a speculative helper thread. Based upon information in the thread progress beacon table, the main thread may effect termination of a helper thread that is not likely to provide a performance benefit for the main thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.