Addressing strategy for Viterbi metric computation
US7818654B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2005 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Feb 14, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6505
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is provided an addressing architecture for parallel processing of recursive data. A basic idea is to store a calculated new path metric at the memory location used by the old path metric, which old metric was employed to calculate the new metric. If m metric values are read and m metric values are simultaneously calculated in parallel, it is possible to store the new, calculated metrics in the memory position where the old metrics were held. This is advantageous, since the size of the storage area for the path metrics is reduced to half compared to the storage area employed in prior art Viterbi decoders for the same performance with regard to path metric computations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.