Tamper response mechanism
US7818799B2 · kind B2 · utility
7Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2006 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Aug 19, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/554
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A tamper response mechanism introduces a delayed failure into a program in response to detected tampering with the program. The mechanism determines a manner of responding to the detected tampering. The manner of responding may include corrupting a global pointer or using other techniques. The mechanism also determines when to respond to the tampering and implements the response at the determined time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.