Layout architecture for improving circuit performance
US7821039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2008 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Apr 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.