Substrate including barrier solder bumps to control underfill transgression and microelectronic package including same
US7821131B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 21, 2007 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Dec 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic substrate and a microelectronic package including the substrate and a die bonded thereto. The substrate includes a substrate panel having a die-side surface including a die-attach region; a system of interconnects extending through the substrate panel and adapted to allow a connection of the substrate to external circuitry; and a plurality of solder bumps including: die-attach solder bumps electrically coupled to the system of interconnects and disposed in the die-attach region; and barrier solder bumps isolated from the system of interconnects, the barrier solder bumps being disposed outside of the die-attach region and being adapted to substantially limit a flow of underfill away from the die-attach region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.