Stacked buffers
US7821296B2 · kind B2 · utility
3Cited by
13References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2006 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Aug 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/5036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Two or more buffers may configured and arranged such that a quiescent current that flows through and biases a first buffer also flows through and biases a second buffer. The first and second buffers may, for example, be source followers used as reference buffers that drive inputs of a switched-capacitor circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.