Comparator and A/D converter
US7821303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2006 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Oct 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/362
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator 100 is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.