Output stage circuit and operational amplifier
US7821340B2 · kind B2 · utility
4Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2009 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Aug 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/297
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output stage circuit is disclosed, which includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. By using twin-well CMOS transistors and a specific circuit configuration, the invention supports a HALF AVDD structure, reduces power consumption and saves the cost of triple-well CMOS process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.