SAR analog-to-digital converter having variable currents for low power mode of operation
US7821441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2008 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Dec 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive approximation analog-to-digital converter includes a capacitor array having a plurality of switch capacitors therein with varying weights, each having a common plate connected to a common node and a switched plate. A SAR controller samples an input voltage on said capacitor array in a sampling phase and redistributes the charge stored therein in a conversion phase by selectively increasing the voltage on select capacitors of the capacitor array in accordance with a SAR conversion algorithm. Circuitry controls the sampling of the input voltage by the capacitor array and is responsive to at least one applied bias current. The at least one applied bias current operates at a first level responsive to a first mode of operation of the SAR ADC and operates at a second level responsive to a second mode of operation of the SAR ADC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.