Display apparatus
US7821487B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2006 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Aug 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and multiple drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit for generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for a delay direction and a delay width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.