Memory access optimization
US7821962B2 · kind B2 · utility
0Cited by
13References
14Claims
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Key dates
| Filing date | Nov 7, 2008 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Apr 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/1097
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for memory access optimization are disclosed. Data unit information may be accumulated for a plurality of data units. Partial network statistics for the plurality of data units may be read sequentially in round robin fashion from each of a plurality of memory banks of a memory. The partial networks statistics may be updated based on the plurality of data units. The updated partial network statistics may be written sequentially in round robin fashion to each of the plurality of memory banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.