Enhanced rake structure
US7822106B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 2004 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Aug 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2201/70707
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A rake architecture for a frequency division duplex (FDD) and use also in TDD and TD-SCDMA type communications system, designed to significantly reduce the memory capacity required and thereby also reduce an area on the die of an application specific integrated circuit (ASIC) into which the memory is integrated. A single circular buffer, preferably of the shared memory type is shared by all of the rake fingers of a rake receiver to significantly reduce the hardware and software required to time align multipath signals received by a UE from a base station. This unique time alignment technique also reduces the number of code generators required to track a plurality (typically three) of base stations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.