Voltage referencing clock for source-synchronous multi-level signal buses
US7823003B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 23, 2007 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Jul 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input circuit is provided for coupling to a source-synchronous multi-level bus carrying data, clock, and complementary clock signals. The clock and complementary clock signals have a less than full voltage swing than the data signal so they can act as reference voltages for the data signal. The circuit includes a first differential receiver having inputs coupled to the data and the clock signals, a second differential receiver having inputs coupled to the data signal and a reference signal, and a third differential receiver having inputs coupled to the data and the complementary clock signals. The circuit further includes first, second, and third flip-flops having data inputs coupled to outputs of the first, the second, and the third differential receivers, and clock inputs coupled to a delayed clock signal generated from the clock and the complementary clock signals. The outputs of the flip-flops determine the level of the data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.