Hardware data race detection in HPCS codes
US7823013B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2007 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Feb 7, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0886
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for detecting race conditions computing systems. A parallel computing system includes multiple processor cores is coupled to memory. An application with a code sequence in which parallelism to be exploited is executed on this system. Different processor cores may operate on a given memory line concurrently. Extra bits are associated with the memory data line and are used to indicate changes to corresponding subsections of data in the memory line. A memory controller may perform a comparison between check bits of a memory line to determine if more than one processor core modified the same section of data in a cache line and a race condition has occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.