Method for streamlining error connection code computation while reading or programming a NAND flash memory
US7823044B2 · kind B2 · utility
9Cited by
12References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 26, 2004 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Sep 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for streamlining error correction code computation while reading or programming a NAND flash memory. At least some of the illustrative embodiments are methods comprising transferring a data block between a flash memory and a memory controller, and computing an ECC for said data block while transferring the data block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.