Compilable, reconfigurable network processor
US7823091B2 · kind B2 · utility
5Cited by
1References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 27, 2006 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Jul 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor, particularly a network processor, is designed by first writing code to be processed by the processor. That code is then electronically compiled to design hardware of the processor and to provide executable code for execution on the designed hardware. To facilitate compilation, the written code may be restricted by predefined functional units to be implemented in hardware, and the executable code may include very long instruction word code. The functional units may be implemented in reconfigurable circuitry or custom circuitry, and the designed hardware may include combinational logic in reconfigurable circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.