Unrolling hardware design generate statements in a source window debugger
US7823097B2 · kind B2 · utility
1Cited by
4References
18Claims
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Key dates
| Filing date | Sep 15, 2006 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Aug 17, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3308
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Unrolling the “generate” statement of a hardware description language (“HDL”) and displaying the unrolled HDL. For a conditional generate the condition is evaluated. If the statement is true the enclosed HDL code will be displayed. For an iterative generate, the enclosing HDL will be displayed as many times as specified by the bounds of the iteration scheme. This allows, for example, simulation value annotations for signals declared inside the generate statement, semantic navigation inside the generate statements, and allows the user to visualize what is included in the target design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.