Automatic integrated circuit routing using spines
US7823113B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2006 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | May 20, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.