Multi-metal-oxide high-K gate dielectrics
US7824990B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2006 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Apr 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.