Phase locked loop that sets gain automatically
US7825706B2 · kind B2 · utility
9Cited by
27References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2004 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Sep 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is provided a phase locked loop, PLL, that sets gain automatically. The PLL comprises a frequency discriminator for providing a first signal that represents the difference between a first frequency and a second frequency. The PLL also comprises a comparator coupled to the frequency discriminator for receiving the first signal and providing a second signal based on information from the first signal. The second signal is representative of a gain setting for the phase locked loop to set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.