Tri-state delay-typed phase lock loop
US7825709B2 · kind B2 · utility
1Cited by
11References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2009 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | May 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a tri-state delay-typed phase lock loop, which comprises: a phase and frequency detector, a mode detector, a mode selector, a first sampling delay unit, a plurality of counters, a second sampling delay unit, and a phase and frequency calculator. The phase and frequency of the input reference signal can be determined automatically by the phase lock loop, and the output synchronization signal can be generated such that the frequency and the phase of the output synchronization signal are identical to those of the input reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.