Limit equalizer output based timing loop
US7825836B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2008 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Jan 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.