Semiconductor memory device that can relieve defective address
US7826241B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2008 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Jan 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pre-decoded address is generated at a high speed in a semiconductor memory device. The device comprises a pre-decoder (210) for generating a first pre-decoded address (PDA1) by pre-decoding the input address (ADD), a CAM circuit (220) for activating the match signal (MT) by responding to the indication of a defective memory cell by the input address (ADD), a ROM circuit (230) for outputting a second pre-decoded address (PDA2) and an enable signal (ES) in response to the activation of the match signal (MT), and a multiplexer (240) for selecting either the first or second pre-decoded address (PDA1 or PDA2) on the basis of the enable signal (ES). According to the present invention, there is no need to use a circuit with numerous stages as there is in substituted logic; accordingly, pre-decoded addresses can be generated at a high speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.