Row decoder for a memory device
US7826302B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2008 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Apr 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device including an array of memory cells arranged in a plurality of rows and in a plurality of columns. The memory device further includes a plurality of word lines each associated with a respective row of the array and identified by a respective row address, and a row decoder configured to receive a current row address and select a word line according to said current row address. The row decoder includes a plurality of row selection units each associated with a respective word line and configured to receive the current row address; each row selection unit is configured to be enabled for biasing the respective word line to a selection voltage if the current row address identifies said word line. Each row selection unit includes a corresponding enabling device for enabling the row selection unit after a predetermined time from the reception of the current row address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.