Asynchronous line interface rate adaptation to the physical layer with synchronous lines at the connection layer
US7826488B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2006 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Jan 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2007/045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for adapting the rates of a certain number of asynchronous HDLC channels (15) to a single clock domain suited for interfacing with an HDLC processor (13) through a synchronous pseudo-TDM interface (14) in which the HDLC channels are multiplexed in time and vice versa in the opposite direction. In one direction the algorithm is based on the writing of the HDLC channels in a dedicated buffer (17) and in reading these buffers with a common synchronous clock just above the expected maximum HDLC rate. The under-run condition is avoided by inserting neutral information between the end byte and the start byte of the HDLC packets when this is suggested by the buffer fill monitoring function. A simple function to locate the first and last bytes of each HDLC packet read by the buffer is hence used in combination with the buffer fill monitoring function. The algorithm is also suited in the opposite direction in which different asynchronous physical lines receive their HDLC channels from a synchronous TDM-type interface on condition that this interface clock domain be just below the minimum expected HDLC output rate. In this case also the under-run conditions are avoided by insertion …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.