Method to secure an electronic assembly against attacks by error introduction
US7826610B2 · kind B2 · utility
1Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2003 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Jun 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/127
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention concerns a method to secure an electronic assembly implementing any algorithm against attacks by error introduction. The method according to the invention consists in performing an additional calculation using a verification function on at least one intermediate result in order to obtain a calculation signature and in performing a least once more all or part of the calculation in order to recalculate said signature and compare them in order to detect a possible error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.