Method and apparatus for increasing the efficiency of an emulation engine
US7827023B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2006 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Sep 23, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for a memory efficient hardware emulator. The emulator comprises a plurality of processor dusters having data within the duster is stored in at least one data array, where the at least one data array comprises a plurality of sub-arrays. The sub-arrays that are not of uniform size (e.g., the size of each sub-array is determined by the probability that a particular sub-array will be accessed by the processor during a future emulation step). For example, at least one first sub-array is equal in depth to instruction memory within a processor (i.e., equal to the number of instructions in an emulation cycle), and the remaining sub-arrays are a fractional depth of the first sub-array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.