Low latency, high bandwidth data communications between compute nodes in a parallel computer
US7827024B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2007 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | May 31, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4269
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, parallel computers, and computer program products are disclosed for low latency, high bandwidth data communications between compute nodes in a parallel computer. Embodiments include receiving, by an origin direct memory access (‘DMA’) engine of an origin compute node, data for transfer to a target compute node; sending, by the origin DMA engine of the origin compute node to a target DMA engine on the target compute node, a request to send (‘RTS’) message; transferring, by the origin DMA engine, a predetermined portion of the data to the target compute node using memory FIFO operation; determining, by the origin DMA engine whether an acknowledgement of the RTS message has been received from the target DMA engine; if the an acknowledgement of the RTS message has not been received, transferring, by the origin DMA engine, another predetermined portion of the data to the target compute node using a memory FIFO operation; and if the acknowledgement of the RTS message has been received by the origin DMA engine, transferring, by the origin DMA engine, any remaining portion of the data to the target compute node using a direct put operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.