Intergrated circuit and a method of cache remapping
US7827372B2 · kind B2 · utility
414Cited by
15References
20Claims
0Family size
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Key dates
| Filing date | Aug 17, 2004 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Jan 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is provided with at least one processing unit (TM), a cache memory (L2 BANK) having a plurality of memory modules, and remapping means (RM) for performing an unrestricted remapping within said plurality of memory modules. Accordingly, faulty modules can be remapped without limitations in order to optimise the utilization of the memory modules by providing an even distribution of the faulty modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.