Communication bus with hidden pre-fetch registers
US7827387B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2006 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | May 27, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0676
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-on-chip (SOC) includes a processor, a controller module for a hard disk drive, and a communication bus that provides a communication link between the processor and the controller module. The communication bus includes a multiplexer that includes an output and an input that receives data from a selected one of N registers associated with the controller module and propagates the data to the output, M address registers that store addresses of up to M ones of the N registers, M data registers that receive pre-fetch data that corresponds to the data from the output from the M ones of the N registers, and a second multiplexer that includes a second output and that reads the pre-fetch data from the M data registers and propagates the pre-fetch data to the second output. M and N are positive integers greater than two and N is greater than M.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.