Through-wafer vias
US7829462B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2007 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Dec 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A through-wafer via interconnect region is in a circuit portion of a wafer, the circuit portion including at least one electrically conducting metal layer and configured for use, after dicing of the wafer, as one of a plurality of layers stacked vertically to form a three dimensional integrated circuit. Within the metal layer in the circuit portion, the metal is removeably distributed such that the ratio of metal to nonmetal area, within the via region, varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.