Layout for self-aligned emitter-base processing
US7829917B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 14, 2007 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Jun 23, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/126
Abstract
The present invention provides a layout for a self-aligned semiconductor device, comprising an emitter mesa structure having an emitter electrode, and a base region that is comprised of a base electrode, with the base electrode deposited along crystal planes of the emitter mesa structure that undercut when the emitter mesa structure is etched, while avoiding depositing of the base electrode along crystal planes of the emitter mesa structure that do not undercut when the emitter mesa structure is etched. This allows the emitter electrode and the base electrode to self-align along the crystal planes that the emitter mesa structure undercuts when etched, and be isolated along the crystal planes that the emitter mesa structure does not undercut when etched. The present invention further provides dual interconnects mechanism and for connecting external circuitry to various semiconductor layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.