Semiconductor device and manufacturing method thereof
US7829957B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2008 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Oct 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/84
Abstract
A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET on the same semiconductor substrate includes: a first threshold adjustment layer for adjusting threshold of the E-FET; a first etching stopper layer formed on the first threshold adjustment layer; the second threshold adjustment layer formed on the first etching stopper layer for adjusting threshold of the D-FET; a second etching stopper layer formed on the second threshold adjustment layer; a first gate electrode penetrating through the first etching stopper layer, the second threshold adjustment layer, and the second etching stopper layer, which is in contact with the first threshold adjustment layer; and the second gate electrode penetrating through the second etching stopper layer, which is in contact with the second threshold adjustment layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.