Patent · US Active

Method and apparatus for universal program controlled bus architecture

US7830173B2 · kind B2 · utility

3Cited by

93References

20Claims

0Family size

Assignee

Actel Corporation · US

Inventors

Peter M. Pani · Mountain View, US
Benjamin S. Ting · Saratoga, US

Key dates

Filing date	Mar 10, 2009
Grant date	Nov 9, 2010
Priority date	—
Expiry date	Mar 10, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17796
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.