Comparator with reduced power consumption
US7830183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2008 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Feb 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator component having a comparison circuit and bias generator circuit, with the bias generator circuit also having a same number of transistors connected in an identical configuration, as those contained in the comparison circuit to generate a comparison result based on the bias signal generated by the bias generator circuit. A transistor of the comparison circuit receiving the bias signal is connected to a corresponding transistor in the bias generator circuit, in a current mirror configuration. The same bias circuit may be shared by many comparison circuits of corresponding comparator components. The features can be extended to provide hysteresis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.