Dynamically-driven deep n-well circuit
US7830199B2 · kind B2 · utility
1Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2008 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Jul 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, and a first well switch configured to selectively connect the n-well to a predetermined voltage in response to an enable phase of a first switching signal. The first well switch can be configured to connect the n-well to the predetermined voltage during the enable phase of the first switching signal and to electrically float the n-well during a non-enable phase of the first switching signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.