Parallel bit interleaver for a wireless system
US7830957B2 · kind B2 · utility
13Cited by
5References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2006 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Jan 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0093
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided to process wireless data packets. A method includes determining a subset of data bits to be processed at a wireless transmitter and employing a clock edge to store the data. The clock edge allows parallel mapping of at least two bits from the subset of data bits into an interleaver memory per a given clock edge. From the memory, other encoding and scrambling processes are applied before transmitting the data packets across a wireless network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.